1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits, and, more particularly, an improvement in buffer circuits for receiving input signals.
2. Description of the Background Art
The BiCMOS technology has been so far developed in which an ECL (Emitter Coupled Logic) circuit capable of a high-speed operation and having a high load drive capability and a CMOS circuit of less power consumption are combined.
FIG. 17A is a circuit diagram showing a first conventional ECL buffer circuit for receiving a signal of an ECL level.
In FIG. 17A, an input portion comprises a bipolar transistor Q1, a level shifting diode D1 and a constant current source CS1. The base of the transistor Q1 receives an input signal Vin of an ECL level. The collector of the transistor Q1 is connected to a ground terminal receiving a ground voltage V.sub.cc while the emitter is connected to a node N1 through the diode D1. The constant current source CS1 is connected between the node N1 and a power supply terminal receiving a negative voltage V.sub.EE.
A resistor R1 and a bipolar transistor Q2 form a first switch circuit, and a resistor R2 and a bipolar transistor Q3 form a second switch circuit. A current switch portion comprises a first and a second switch circuits and a constant current source CS2. The resistor R1 is connected between the ground terminal and a node N4. The collector of the transistor Q2 is connected to the node N4, the emitter is connected to the node N2, and the base is connected to the node N1. The resistor R2 is connected between the ground terminal and a node N5. The collector of the transistor Q3 is connected to the node N5, the emitter is connected to the node N2, and the base receives a reference voltage V.sub.BB. The constant current source CS2 is connected between the node N2 and the power supply terminal.
The first output circuit comprises an emitter follower bipolar transistor Q4, and the second output circuit comprises an emitter follower bipolar transistor Q5. An output portion comprises a first and a second output circuits and constant current sources CS3, CS4. The collector of the transistor Q4 is connected to the ground terminal, the emitter is connected to the node N6, and the base is connected to the node N4. The constant current source CS3 is connected between the node N6 and the power supply terminal. The collector of the transistor Q5 is connected to the ground terminal, the emitter is connected to a node N7, and the base is connected to the node N5. The constant current source CS4 is connected between the node N7 and the power supply terminal. An output signal a (NOR output) is output from the node N6, and an output signal a (OR output) is output from the node N7.
The logically high level (hereinafter referred to as H level) of the input signal Vin of an ECL level is normally -0.9 V, and the logically low level (hereinafter referred to as L level) of that is normally -1.7 V. The reference voltage V.sub.BB is set so as to be an intermediate voltage between an H level and an L level of the base voltage of the transistor Q2.
The operation of the ECL buffer circuit of FIG. 17A will now be described with reference to a waveform diagram of FIG. 17B.
When the level of the input signal Vin changes from an L level to an H level, the level of the base voltage of the transistor Q2 also changes to an H level. Consequently, the transistor Q2 turns on, and the transistor Q3 turns off. As a result, the base voltage (the voltage of the node N4) of the transistor Q4 attains an L level indicated by V.sub.cc -R.sub.1 .multidot.I2, where R.sub.1 is the value of the resistance of R1, and I2 is a current flowing through the constant current source CS2. Also, the base voltage (the voltage of the node N5) of the transistor Q5 almost attains an H level indicated by V.sub.CC.
Accordingly, the output signal a from the node N6 attains an L level indicated by of V.sub.CC -V.sub.BE -R.sub.1 .multidot.I2. The output signal a from the node N7 attains an H level indicated by of V.sub.CC -V.sub.BE.
Conversely, when the level of the input signal Vin changes from an H level to an L level, the output signal a attains an H level indicated by V.sub.CC -V.sub.BE, and the output signal a attains an L level indicated by V.sub.CC -V.sub.BE -R.sub.2 .multidot.I2, where R.sub.2 is the resistance value of the resistor R2.
FIG. 18A is a circuit diagram of a second conventional ECL buffer circuit.
In the ECL buffer circuit of FIG. 18A, the constant current source CS4, which is included in the output portion of the ECL buffer circuit of FIG. 17A, is eliminated for lower power consumption. The output portion is further provided with bipolar transistors Q6, Q7. The collector of the transistor Q6 is connected to the node N6, and the base is connected to the node N1. The collector of the transistor Q7 is connected to the node N7, and the base receives the reference voltage V.sub.BB. The emitters of the transistors Q6, Q7 are each connected to the constant current source CS3 through the node N3.
The operation of the ECL buffer circuit of FIG. 18A will now be described with reference to a waveform diagram of FIG. 18B.
When the level of the input signal Vin changes from an L level to an H level, the levels of the base voltages of the transistors Q2, Q6 changes to an H level. Thus, the transistors Q2, Q6 turn on, and the transistors Q3, Q7 turn off. As a result, the voltage
of the node N4 attains an L level indicated by V.sub.CC -R.sub.1 .multidot.I2, and the voltage of the node N5 attains an H level indicated by V.sub.CC.
Therefore, the output signal a attains an L level indicated by V.sub.CC -V.sub.BE -R.sub.1 .multidot.I2, and the output signal a attains an H level indicated by V.sub.CC -V.sub.f, where, V.sub.f indicates the base-emitter voltage of the NPN transistor when there is little electric current in the NPN transistor, which attains a value smaller than that of the base-emitter voltage V.sub.BE of the NPN transistor in a normal on-state (V.sub.f &lt;V.sub.BE).
When the level of the input signal Vin changes from an H level to an L level, the output signal a attains an H level indicated by V.sub.CC -V.sub.f, and the output signal a attains an L level indicated by V.sub.CC -V.sub.BE -R.sub.2 .multidot.I2.
FIG. 19A is a circuit diagram of a third conventional ECL buffer circuit.
In the ECL buffer circuit of FIG. 19A, there no emitter follower bipolar transistors Q4, Q5 and no constant current sources CS3, CS4 of the ECL buffer circuit shown in FIG. 17A, the output signal a is output from the node N4, and the output signal a is output from the node N5.
The operation of the ECL buffer circuit of FIG. 19A will now be described with reference to a waveform diagram of FIG. 19B.
In the ECL buffer circuit of FIG. 19A, the emitter follower transistors Q4, Q5 of FIG. 17A are removed, and output signals a, a are output respectively from the nodes N4, N5, so that, as described in FIG. 17A, the H level of the output signals a, a from the nodes N4, N5 is equal to the ground voltage V.sub.CC, and the L level of that is equal to V.sub.CC -RL1.multidot.I2, where RL1 indicates R or R.sub.2.
FIG. 20A is a circuit diagram of a fourth conventional ECL buffer circuit.
In the ECL buffer circuit of FIG. 20A, resistors R25, R26, R27 are connected in place of the resistors R1, R2 in the ECL buffer circuit of FIG. 19A. One terminals of the resistors R26, R27 are connected to the nodes N4, N5, respectively, and the other terminals are connected to the ground terminal through the resistor R25. In the ECL buffer circuit of FIG. 20A, as shown in the waveform diagram of FIG. 20B, the value of the H level of the output signals a, a becomes low. This value of the H level can be set to any value by changing the resistance values of the resistors R25 to R27.
The ECL buffer circuit of FIG. 17A is disclosed, for example, in "the development of 6 ns/800 mW 64 K.times.1 BiCMOS ECL RAM", Technical Research Report of the Institute of the Electronics, Information and Communication Engineers of Japan Vol, 89, No. 140, pp. 13-18. The ECL buffer circuit of FIG. 18A is disclosed, for example, in the above Technical Research Report of the Institute the Electronics, Information and Communication Engineers of Japan and in Japanese Patent Laying-Open No. 59-115620. In addition, the ECL buffer circuit of FIG. 19A is disclosed, for example, by I. Fukushi, et al in "A 256Kb ECL RAM with Redundancy", 1988 ISSCC, pp. 134-135 (Feb. 1988) and in Japanese Patent Laying-Open No. 62-123825.
FIG. 21 shows an example where the ECL buffer circuit of FIG. 17A is connected to the BiCMOS driver circuit over a level converting circuit.
In FIG. 21, the output signals a, a of the ECL buffer circuit 10 of FIG. 17A are supplied to a level converting circuit 20a comprising two current mirror circuits, and the output signals b, b of the level converting circuit 20a are connected to a BiCMOS driver circuit 30 comprising a composite circuit of a bipolar transistor and a CMOS.
The level converting circuit 20a comprises a first current mirror circuit having PMOS transistors MP1, MP2 and NMOS transistors MN1, MN2, and a second current mirror circuit having PMOS transistors MP3, MP4 and NMOS transistors MN3, MN4. The gates of the transistors MP1, MP4 are provided with the output signal a, and the gates of the transistors MP2, MP3 are provided with the output signal a. An output signal b of an MOS level is output from the node of the transistor MP2 and the transistor MN2, and an output signal b of an MOS level is output from the node of the transistor MP4 and the transistor MN4.
The BiCMOS driver circuit 30 comprises a first CMOS inverter having a PMOS transistor MP5 and an NMOS transistor MN5, a second CMOS inverter having a PMOS transistor MP6 and an NMOS transistor MN8, a first base control circuit having NMOS transistors MN6 and MN7, a second base control circuit having NMOS transistors MN9 and MN10, and NPN transistors QD1 to QD4. The transistors QD1, QD2 and the transistors QD3, QD4 are totem-pole-connected respectively between a ground terminal receiving the ground voltage V.sub.CC and the power supply terminal receiving a negative voltage V.sub.EE.
When the level of the input signal Vin of an ECL level changes from an L level to an H level, as described in FIG. 17A, the level of the output signal a of the ECL buffer circuit 10 changes from an L level to an H level, and the level of the output signal a changes from an H level to an L level.
Therefore, the transistors MP1, MP4 of the level converting circuit 20a turn off, and the transistors MP2, MP3 turn on. The current from the ground terminal is thereby cut off by the transistor MP1 so that the voltage of the drain and the gate of the transistor MN1 is lowered to V.sub.EE +Vtn, causing the transistor MN1 to turn off where Vtn is a threshold voltage of the NMOS transistor. The gate of the transistor MN2 is connected to the gate and the drain of the transistor MN1 so that the transistor MN2 turns off. Since the voltages of the gate and the drain of the transistor MN3 increase, the transistor MN3 turns on. Since the gate of the transistor MN4 is connected to the gate and the drain of the transistor MN3, the transistor MN4 also turns on.
The transistor MP2 is on and the transistor MN2 is off, so that the level of the output signal b of the level converting circuit 20a changes from an L level (negative voltage V.sub.EE) to an H level (ground voltage V.sub.CC). The transistor MP4 is off and the transistor MN4 is on, so that the level of the output signal b changes from an H level (ground voltage V.sub.CC) to an L level (negative voltage V.sub.EE). The levels of these output signals b, b are adapted for an MOS level. The conversion from an ECL level to an MOS level is, therefore, carried out.
As the level converting circuit 20a comprises a MOS transistor, its load drive capability is not so high, and thus, it is necessary to increase the drive capability by way of the BiCMOS driver circuit 30 in the next stage.
As described above, when the level of the output signal b changes to an H level, the transistor MP5 turns off, and the transistors MN5, MN6 turn on. The transistor MN7 turns off. Therefore, the transistor QD1 turns off, and the transistor QD2 turns on. Consequently, a signal c output from the BiCMOS driver circuit 30 attains an L level, (V.sub.EE +V.sub.f).
When the level of the output signal b changes to an L level as stated above, the transistor MP6 turns on, and the transistors MN8, MN9 turn off. The transistor MN10 turns on. Accordingly, the transistor QD3 turns on, and the transistor QD4 turns off. As a result, a signal c output from the BiCMOS driver circuit 30 attains an H level (V.sub.CC -V.sub.f). The level of these signals c, c is referred to as a BiCMOS level.
As above mentioned, a conversion of the logic level is carried out between an ECL circuit and a MOS circuit.
The level converting circuit 20b shown in FIG. 22 or the level converting circuit 20c shown in FIG. 23 may be used in place of the level converting circuit 20a shown in FIG. 21.
In FIG. 22, the output signal a of the ECL buffer circuit is supplied to the gates of the PMOS transistors MP7, MP10, and the output signal a is supplied to the gates of the PMOS transistors MP8, MP9. The sources of the transistors MP7, MP9 are connected to the ground terminal, and the drains of the transistors MP8, MP10 are connected to the power supply terminal. While the drain of the transistor MP7 and the source of the transistor MP8 are connected to the drain of the NMOS transistor MN11 and the base of the bipolar transistor QCI, the drain of the transistor MP9 and the source of the transistor MP10 are connected to the drain of the NMOS transistor MN14 and the base of the bipolar transistor QC2.
The collectors of the transistors QC1, QC2 are connected to the ground terminal, and the sources of the NMOS transistors MN11, MN12, MN13, MN14 are connected to the power supply terminal. The emitter of the transistor QC1 is connected to the drain of the transistor MN12 and the gates of the transistors MN13, MN14, and the emitter of the transistor QC2 is connected to the drain of the transistor MN13 and the gates of the transistors MN11, MN12. The output signal b of the level converting circuit 20b is output from the emitter of the transistor QC2, and the output signal b is output from the emitter of the transistor QC1.
The operation of the level converting circuit 20b of FIG. 22 will now be described.
When the level of the output signal a of the ECL buffer circuit changes from an L level to an H level, and the level of the output signal a changes from an H level to an L level, then the transistors MP7, MP10 turn off, and the transistors MP8, MP9 turn on. Accordingly, the potential of the drain of the transistor MP7 rises, and the potential of the drain of the transistor MP9 falls.
Thus, the transistor QCI starts turning off, and the transistor QC2 starts turning on. Then, the emitter of the transistor QC2 is charged rapidly and the gate voltages of the transistors MN11, MN12 rise, causing their transistors to turn on, whereby the transistor QC1 and the transistors MN13, MN14 turn off.
Since the transistor QC2 is on, and the transistor MN13 is off, the level of the output signal b changes from an L level (negative voltage V.sub.EE) to an H level (ground voltage V.sub.CC -V.sub.f). Since the transistor QC1 is off and the transistor MN12 is on, the level of the output signal b changes from an H level (ground voltage V.sub.CC -V.sub.f) to an L level (negative voltage V.sub.EE).
Conversely, when the level of the output signal a of the ECL buffer circuit changes from an H level to an L level, and the level of the output signal a changes from an L level to an H level, then the level of the output signal b changes from an H level to an L level, and the level of the output signal b changes from an L level to an H level, which is the reverse operation to the aforementioned.
In FIG. 23, the output signal a of the ECL buffer circuit is supplied to the gates of the PMOS transistor MP11 and the NMOS transistor MN15, and the output signal a is supplied to the gates of the PMOS transistor MP12 and the NMOS transistor MN17. The sources of the transistors MP11, MP12 are connected to the ground terminal. The sources of the NMOS transistors MN16, MN18 are connected to the power supply terminal. The gate of the transistor MN16 is connected to the drain of the transistor MP12, and the gate of the transistor MN18 is connected to the drain of the transistor MP11. The source of the transistor MN15 is connected to the drain of the transistor MN16, and the drain of the transistor MN15 is connected to the drain of the transistor MP11. The source of the transistor MN17 is connected to the drain of the transistor MN18, and the drain of the transistor MN17 is connected to the drain of the transistor MP12. The output signal b of the level converting circuit 20c is output from the drain of the transistor MP12, and the output signal b is output from the drain of the transistor MP11.
The operation of the level converting circuit 20c of FIG. 23 will now be described.
When the level of the output signal a of the ECL buffer circuit changes from an L level to an H level and the level of the output signal a changes from an H level to an L level, then the transistor MP11 turns off, and the transistor MP12 turns on. In addition, the on-resistance of MN15 is lowered, and the on-resistance of the transistor MN17 is increased. Therefore, the current of the transistor MP12 causes the potential of the drain to rise. At this time, it is possible to decrease the percentage of the feed-through current of the current flowing in the transistor MP12 since the on-resistance of the transistor MN17 is high.
The rise of the drain potential of the transistor MP12 causes the transistor MN16 to turn on, and the potential of the drain of the transistor MP11 to be decreased through the transistor MN15 of low on-resistance. Thus, the transistor MN18 turns off, and there is little feed-through current in the transistors MP12, MN17. Accordingly, the level of the output signal b changes from an L level (negative voltage V.sub.EE) to an H level (ground voltage V.sub.CC), and the level of the output signal b changes from an H level to an L level.
Conversely, when the level of the output signal a changes from an H level to an L level, and the level of the output signal a changes from an L level to an H level, then the level of the output signal b changes from an H level to an L level, and the level of the output signal b changes from an L level to an H level.
The level converting circuit 20a in FIG. 21 is disclosed, for example, in Japanese Patent Laying-Open No. 60-132416 and in Japanese Patent Laying-Open No. 62123825. The level converting circuit 20b in FIG. 22 is also disclosed for example in the above-mentioned literature 1988 ISSCC, pp. 134-135. In addition, the level converting circuit 20c in FIG. 23 is disclosed for example in the above Technical Research Report of the Institute of the Electronics, Information and Communication Engineers of Japan, Vol. 89, No. 140, pp. 13-18 and in the prior filed Japanese Patent Application No. 1-127113.
As described above, the H level of the output signals a, a of the ECL buffer circuit in FIG. 17A become V.sub.CC -V.sub.BE. In the level converting circuit 20a in FIG. 21, when the PMOS transistor, which is provided with an output signal of an H level from the ECL buffer circuit, completely turns off, it becomes possible to full-swing the output signals b, b from the ground voltage V.sub.CC to the negative voltage V.sub.EE with small feed-through current.
However, as shown in FIG. 17B, the H level of the output signals a, a reaches no more than -0.8 V since the base-emitter voltage V.sub.BE of the NPN transistor is normally set to 0.8 V. The threshold voltage Vtp of the PMOS transistor of the level converting circuit 20a is normally set to about -0.7 V. It therefore leads to V.sub.CC -V.sub.BE &lt;Vtp, so that the gate-source voltage of the PMOS transistor, which is provided with the output signal of an H level, exceeds its threshold voltage. As a result, the PMOS transistor, which is essentially to turn off completely, turns on lightly so that a relatively large amount of feed-through current flows.
For example, in FIG. 21, when the output signal a of the ECL buffer circuit 10 is at an H level and the output signal a is at an L level, then the transistors MP1, MP4 lightly turn on without turning off, and the transistors MP2, MP3 turn on. Accordingly, a large amount of feed-through current flows in the path from the transistor MP1 to the transistor MN1, the path from the transistor MP2 to the transistor MN2 and the path from the transistor MP4 to MN4, where, originally, no large amount of feed-through current should flow.
In this case, the output level of the output signal b depends on the resistance division of the on-resistance of the transistor MP2 and the transistor MN2. The output level of the output signal b depends on the resistance division of the on-resistance of the transistor MP4 and the transistor MN4. Thus, the output level of the output signals b, b reaches an intermediate potential between the ground voltage V.sub.CC and the negative voltage V.sub.EE. Thus, the output amplitude becomes narrower, without causing the output signals b, b to swing from the ground voltage V.sub.CC to the negative voltage V.sub.EE. There is a problem that the output signal rises slowly since direct current also flows in the output stage which provides a signal of an H level.
In addition, if the output level of the output signals b, b becomes an intermediate potential, it causes a large amount of feed-through current to flow also in the BiCMOS driver circuit 30 which receives the output signal b, b.
Thus, the ECL buffer circuit in FIG. 17A entails a problem of large power consumption and a slow rise speed of the output signal.
A problem similar to the above-mentioned also exists in the case in which the ECL buffer circuit of FIG. 17A is connected to either the level converting circuit 20b in FIG. 22 or the level converting circuit 20c in FIG. 23. The problem above becomes more serious particularly in the level converting circuit 20b of FIG. 22 having an output stage of the bipolar transistor. The reason is because the bipolar transistor amplifies the current flowing in the PMOS transistor, which should naturally turn off.
Since there is no current through the emitter follower transistor which provides a signal of an H level in the ECL buffer circuit of FIG. 18A, as shown in FIG. 18B, the output signal a rises rapidly to about -0.7 V, and then is charged very slowly to about the ground voltage (0 V).
Thus, when the time intervals between the first switching of the input signal and the next switching of the input signal differ in a plurality of ECL buffer circuits, the potentials of an H level differ in each ECL buffer circuit. For example, assuming that in one of the two ECL buffer circuits the input signal switches immediately before, and the input signal does not switch for a sufficiently long period of time in the other. In this case, if the input signals supplied to the two ECL buffer circuits switch at the same time, then it results in a skew at a switching timing of the output signals of those ECL buffer circuits. If the ECL buffer circuit is applied to a memory circuit, then such a skew leads to a state in which another memory cell is erroneously selected transitionally at a switching time of the address. Therefore, there is a problem that the access speed must be made slow.
In the ECL buffer circuit of FIG. 19A, the H level of the output signals a, a is equal to the ground voltage V.sub.CC as shown in FIG. 19B, so that the PMOS transistor, which is provided with its output signal, completely turns on.
The load capacity, however, which is provided with the output signals a, a is charged through the resistors R1, R2 so that the waveforms of the output signals a, a slowly change. Therefore, the switching speed of the level converting circuit in the next stage becomes slow. The larger the amplitude of the output of the ECL buffer circuit is made, the more significant the delay of the switching speed becomes.
As the ECL buffer circuit of FIG. 19A has no emitter follower transistor, it is encountered with a problem of a low load drive capability.
The ECL buffer circuit of FIG. 20A, as well as the ECL buffer circuit of FIG. 19A, has a problem that it has a slow switching speed and low load drive capability.
In consideration of the conventional ECL buffer circuit mentioned above, the characteristics desired for an ECL buffer circuit connected to a level converting circuit are as follows:
(1) The H level of the output signal becomes higher than the threshold voltage of the PMOS transistor driven thereby;
(2) The output signal switches rapidly;
(3) The load drive capability is high;
(4) The output potential is constant when a certain period of time has passed which is shorter than the cycle time.